In order to transmit and receive digital signals between LSIs, it is necessary to determine each data bit on the receiving side at a correct time. As such, a signal line for transmitting timing signals (clock signals) is often provided, besides a signal line for transmitting data. However, as it is necessary to provide a timing signal line along a date signal line, an area to be used on a substrate increases. As such, in recent high-speed serial transmission or the like, a timing signal line is eliminated, and a timing signal is superposed on a data signal and transmitted in the transmission side, while in the receiving side, edges of the data signal are detected and the phase of a reference clock is adjusted to thereby reproduce timing information. This process is generally called Clock Data Recovery (CDR), and a circuit provided to the receiving side for Clock Data Recovery is called a CDR circuit.
Main configuration methods of a CDR circuit include a phase-locked loop method, a ring oscillator method, and a phase interpolation method. While each method has advantages and disadvantages, a phase interpolation method is increasingly adopted recently, as the transmission speed is improved (for example, see “Phase Interpolator Based CDR” (Non-Patent Document 1)).
In the phase interpolation method, a CDR circuit generates one or more clocks of arbitrary phases through phase interpolation from a plurality of reference clocks having a fixed phase, and selects an optimum clock phase according to the timing of an edge or the like of a data signal. FIG. 15 is a block diagram showing an exemplary CDR circuit of a phase interpolation method.
Referring to FIG. 15, a CDR circuit 100 includes a multiphase clock generation circuit 110 incorporating a phase selection circuit and a phase interpolation circuit therein, a sampler 120, and a CDR controller 130. The sampler 120 uses a recovery clock generated by the multiphase clock generation circuit 110 to sample received serial data, and outputs an edge sample and a data sample. The CDR controller 130 determines an optimum phase of a clock for sampling serial data according to the edge sample and the data sample, and generates two types of control signals, which are a phase selection signal and a PI selection signal, in order to allow a recovery clock conforming to the determined phase to be generated by the multiphase clock generation circuit 110. The multiphase clock generation circuit 110 selects two sets of clocks, each of which includes two clocks having a phase difference of 90°, among four types of reference clocks of 0°, 90°, 180°, and 270°, according to the phase selection signal. Further, for the respective selected sets, the multiphase clock generation circuit 110 interpolates the two clocks of different phases to generate four clocks having phases determined by the PI selection signal, and outputs the generated clocks to the sampler 120 as recovery clocks.
FIG. 16 is a block diagram showing an example of the multiphase clock generation circuit 110. Referring to FIG. 16, the multiphase clock generation circuit 110 related to the present invention includes four clock input terminals IN0 to IN3, four buffer circuits 111-1 to 111-4, a phase selection circuit 112, two phase interpolation circuits 113-1 and 113-2, and four clock output terminals OUT0 to OUT3. To the clock input terminals IN0 to IN3, four types of reference clocks of 0°, 90°, 180°, and 270° are input. The reference clocks input to the respective clock input terminals IN0 to IN3 are branched into two by the buffer circuits 111-1 to 111-4, and are input as a system-0 input consisting of four types of reference clocks of 0°, 90°, 180°, and 270° and a system-1 input consisting of four types of reference clocks of 0°, 90°, 180°, and 270°, to the phase selection circuit 112. The phase selection circuit 112 selects two sets of clocks, each including two clocks having a phase difference of 90° from each other, from the system-0 input and the system-1 input by a 4-bit phase selection signal SELC[3.0], and outputs the sets to the phase interpolation circuits 113-1 and 113-2. The phase interpolation circuits 113-1 and 113-2 interpolate the input two clocks having a phase difference of 90° from each other, and outputs clocks of phases determined by a PI selection signal SELP[15:0] from the clock terminals OUT0 to OUT3.
The multiphase clock generation circuit 110 shown in FIG. 16 is able to control phases of output clocks at intervals of 5.6° (STEP) in a range of 360° according to combinations of input clocks by the phase selection signal SELC[3:0] and interpolation in the phase interpolation circuits 113-1 and 113-2 by the PI selection signal SELP[15:0].    Non-Patent Document 1: “Phase Interpolator Based CDR”, [online], Rambus, [searched on Oct. 26, 2009], the Internet <URL: http://www.rambus.com/jp/patents/innovations/detail/phase_interpolator.html>    Non-Patent Document 2: “Digital Systems Engineering, Advanced”, Mar. 30, 2003, Maruzen Co. Ltd., pp. 759-761
In order to accurately generates a clock of an intermediate phase from two input clocks having a phase difference of 90° at predetermined intervals with use of a phase interpolation circuit, it is necessary to optimize the transistor size (W/L) inside the phase interpolation circuit and a rise/fall time of a clock waveform to be input to the circuit according to the operating frequency, where W represents a channel width and L represents a channel length. However, it is difficult to optimize the phase interpolation circuit across the entire bandwidth of the operating frequency having a broad bandwidth.
As a measure to address the above problem, there is a compromise in which a phase interpolation circuit is optimized in a high operating frequency, and degradation of capability in low operating frequency is tolerated as not being avoidable. However, in general, when a phase interpolation circuit optimized at a particular operating frequency is used at a lower operating frequency, a phase difference becomes larger and so a waveform distortion becomes larger, whereby intervals between output clock phases become non-uniform. In the worst case, steps may be formed in a waveform of an output clock so as to cause a problem that jitter tolerance is reduced, for example. FIG. 17 shows a simulation result of waveforms of output clocks when an input clock of 5 GHz is input to a phase interpolation circuit optimized at an operating frequency of 5 GHz. Further, FIG. 18 shows a simulation result of waveforms of output clocks when an input clock of 2.5 GHz is input to the same phase interpolation circuit. In FIG. 18, it is found that distortions occur in the output clocks on the way of variation and steps are generated.
Further, as another measure to address the above problem, it may be possible to mount a plurality of phase interpolation circuits optimized at different operating frequencies on a multiphase clock circuit, and switch between the phase interpolation circuits to be used according to an operating frequency. However, this measure involves disadvantages such that the circuit area and the power consumption increase.